4
GATE Pin 6 - This analog output drives the gate of the
external FET used as a pass transistor. The GATE pin is high
(FET is on) when the following conditions are met:
" UVLO is above its trip point (~16.5V)
" Voltage on the UV pin is above its trip point (1.255V)
" Voltage on the OV pin is below its trip point (1.255V)
" No Over-Current conditions are present.
If any of the 4 conditions are violated, the GATE pin will be
pulled low to shut off or regulate current through the FET.
The GATE is latched off only when the 600祍 Over-Current
Time-Out period is exceeded.
The GATE is driven high by a weak (-50礎 nominal) pull-up
current source, in order to slowly turn on the FET. It is driven
low by a 70mA nominal pull-down device for three of the
above shut-off conditions. A larger (350mA nominal) pull-
down current shuts off the FET very quickly in the event of a
hard fault where the sense pin voltage exceeds
approximately 210mV.
DRAIN Pin 7 - This is the analog input to one of two
comparators that control the PWRGD
(ISL6141) or PWRGD
(ISL6151) outputs. It compares the voltage of the external
FET DRAIN to a 1.3V internal reference (V
PG
). The DRAIN
voltage is criticized only until the PWRGD
or PWRGD
outputs are latched into their active low or high states. The
latch is reset when any of the conditions that turn off the
GATE occur (UVLO, OV, UV, OC Time-Out). Note that the
comparator does NOT itself turn off the GATE.
V
DD
Pin 8 - This is the most positive power supply pin. It can
range from the Under-Voltage Lock-Out threshold (16.5V) to
+80V (Relative to V
EE
).
ISL6141, ISL6151
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